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 Durante todo el año recibimos muchos mail, pidiéndonos información para realizar trabajos sobre autómatas. Así que ahora es el momento para recordaros que necesitamos de vuestra colaboración enviándonos los que ya habéis presentado.

      

  

 

FP2 Series

A new dimension
The FP2 offers top performance and a full range of functions at just 36% of the volume of comparable controllers.

Combination CPU with integrated performance

bulletStandard-CPUs
bulletCPU with integrated S-LINK
bulletCombination CPU with 64 inputs
bulletCombination CPU with 4 analogue inputs and 1 analogue output

Up to 28 modules or 1600 (2048) inputs and outputs

bulletThe system allows standard module racks for 5, 7, 9, 12 or 14 modules to be combined.
bulletTo give a total of up to 1600 inputs and outputs (2048 via remote I/O)

Two RS232C interfaces (TOOL port and COM port) included as standard in the CPU

bulletSimple communication with operation display panels or a host PC
bullet115.2kbit/s max. data rate
bulletThe FP2 is of course ready for telecontrol via a modem and offers full remote access functionality 

 

Performance Specifications

 
PLC type
FP2-C1 FP2-C1D FP2-C1A FP2-C1SL
 

Standard type
CPU unit

64-point input
CPU unit
Analogue I/O
CPU unit
S-Link
CPU unit
Inputs/outputs
central: max. 1600 (with 25 modules)
locally expanded: max. 2048 (via MEWNET-F or S-LINK)
Memory
RAM (EPROM or FROM optional)
Programme memory
16,000 steps, expandable to 32,000 steps
Number of instructions
 
basic instructions
96
high-level instructions
428

Operating speed

0.35µs per basic instruction

internal relay (R)

4,048
Memory
timer/counter (T/C)
data register (DT)
data register (DT)
  
1,024
6,000 words
0 to 14,333 words, optionally up to 30,717 words
Master control relay (MCR) 256
Jump labels (JMP + LOOP) 256
Max. main memory programme steps 1,000
Number of subroutines
100

Interrupt programme

1
Time interrupt
0.5ms to 1.5s
Other functions
runtime editing, watchdog function, I/O error check, battery, syntax, memory and password functions, test mode, machine code memory, constant cycle time

 

 

 
 
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        2000, 2006            Última modificación: 02/03/2006